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r8168.changes Changed

r8168.spec Changed

r8168-kernel_5.18.patch Deleted

@@ -1,39 +0,0 @@
----
- src/r8168_n.c |   10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- src/r8168_n.c
-+++ src/r8168_n.c	2022-05-03 21:58:06.034047041 +0000
-@@ -3723,7 +3723,7 @@ static void rtl8168_mac_loopback_test(st
-         txd->opts2 = 0;
-         while (1) {
-                 memset(tmpAddr, pattern++, len - 14);
--                pci_dma_sync_single_for_device(tp->pci_dev,
-+               dma_sync_single_for_device(&tp->pci_dev->dev,
-                                                le64_to_cpu(mapping),
-                                                len, DMA_TO_DEVICE);
-                 txd->opts1 = cpu_to_le32(DescOwn | FirstFrag | LastFrag | len);
-@@ -3751,7 +3751,7 @@ static void rtl8168_mac_loopback_test(st
-                 if (rx_len == len) {
-                         dma_sync_single_for_cpu(tp_to_dev(tp), le64_to_cpu(rxd->addr), tp->rx_buf_sz, DMA_FROM_DEVICE);
-                         i = memcmp(skb->data, rx_skb->data, rx_len);
--                        pci_dma_sync_single_for_device(tp->pci_dev, le64_to_cpu(rxd->addr), tp->rx_buf_sz, DMA_FROM_DEVICE);
-+                        dma_sync_single_for_device(&tp->pci_dev->dev, le64_to_cpu(rxd->addr), tp->rx_buf_sz, DMA_FROM_DEVICE);
-                         if (i == 0) {
- //              dev_printk(KERN_INFO, tp_to_dev(tp), "loopback test finished\n",rx_len,len);
-                                 break;
-@@ -26454,11 +26454,11 @@ rtl8168_init_board(struct pci_dev *pdev,
- 
-         if ((sizeof(dma_addr_t) > 4) &&
-             use_dac &&
--            !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
--            !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
-+            !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
-+            !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
-                 dev->features |= NETIF_F_HIGHDMA;
-         } else {
--                rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
-+                rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
-                 if (rc < 0) {
- #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
-                         if (netif_msg_probe(tp))

r8168-kernel_version.patch Changed

r8168-support-dev0x8136.patch Added

r8168-support-linux-6.1.0.patch Added

@@ -0,0 +1,25 @@
+From 39dd0fd2e5dc45cd63113f33a9890e36c304916d Mon Sep 17 00:00:00 2001
+From: zu1k <i@zu1k.com>
+Date: Sat, 29 Oct 2022 21:57:39 +0800
+Subject: PATCH Adapted for Linux 6.1
+
+---
+ src/r8168.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/src/r8168.h b/src/r8168.h
+index 662974a..baf48c6 100755
+--- a/src/r8168.h
++++ b/src/r8168.h
+@@ -570,7 +570,11 @@ typedef int *napi_budget;
+ typedef struct napi_struct *napi_ptr;
+ typedef int napi_budget;
+ 
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0)
++#define RTL_NAPI_CONFIG(ndev, priv, function, weight)   netif_napi_add(ndev, &priv->napi, function)
++#else
+ #define RTL_NAPI_CONFIG(ndev, priv, function, weight)   netif_napi_add(ndev, &priv->napi, function, weight)
++#endif
+ #define RTL_NAPI_QUOTA(budget, ndev)            min(budget, budget)
+ #define RTL_GET_PRIV(stuct_ptr, priv_struct)        container_of(stuct_ptr, priv_struct, stuct_ptr)
+ #define RTL_GET_NETDEV(priv_ptr)            struct net_device *dev = priv_ptr->dev;

r8168-8.050.03.tar.gz/src/r8168.h -> r8168-8.051.02.tar.gz/src/r8168.h Changed

@@ -190,7 +190,7 @@
 #define NETIF_F_RXFCS  0
 #endif
 
-#ifndef HAVE_FREE_NETDEV
+#if !defined(HAVE_FREE_NETDEV) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0))
 #define free_netdev(x)  kfree(x)
 #endif
 
@@ -344,7 +344,7 @@
 #define DASH_SUFFIX ""
 #endif
 
-#define RTL8168_VERSION "8.050.03" NAPI_SUFFIX FIBER_SUFFIX REALWOW_SUFFIX DASH_SUFFIX
+#define RTL8168_VERSION "8.051.02" NAPI_SUFFIX FIBER_SUFFIX REALWOW_SUFFIX DASH_SUFFIX
 #define MODULENAME "r8168"
 #define PFX MODULENAME ": "
 
@@ -445,6 +445,11 @@
 
 #define OCP_STD_PHY_BASE	0xa400
 
+//Channel Wait Count
+#define R8168_CHANNEL_WAIT_COUNT (20000)
+#define R8168_CHANNEL_WAIT_TIME (1)  // 1us
+#define R8168_CHANNEL_EXIT_DELAY_TIME (20)  //20us
+
 #define NODE_ADDRESS_SIZE 6
 
 #define SHORT_PACKET_PADDING_BUF_SIZE 256
@@ -1387,6 +1392,7 @@
 enum features {
 //  RTL_FEATURE_WOL = (1 << 0),
         RTL_FEATURE_MSI = (1 << 1),
+        RTL_FEATURE_MSIX = (1 << 2),
 };
 
 enum wol_capability {
@@ -1513,6 +1519,8 @@
         struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
         dma_addr_t TxPhyAddr;
         dma_addr_t RxPhyAddr;
+        u32 TxDescAllocSize;
+        u32 RxDescAllocSize;
         struct sk_buff *Rx_skbuffMAX_NUM_RX_DESC; /* Rx data buffers */
         struct ring_info tx_skbMAX_NUM_TX_DESC;   /* Tx data buffers */
         unsigned rx_buf_sz;
@@ -1525,6 +1533,7 @@
         u16 cp_cmd;
         u16 intr_mask;
         u16 timer_intr_mask;
+        int irq;
         int phy_auto_nego_reg;
         int phy_1000_ctrl_reg;
         u8 org_mac_addrNODE_ADDRESS_SIZE;
@@ -1810,7 +1819,7 @@
 #define NIC_RAMCODE_VERSION_CFG_METHOD_28 (0x0019)
 #define NIC_RAMCODE_VERSION_CFG_METHOD_29 (0x0055)
 #define NIC_RAMCODE_VERSION_CFG_METHOD_31 (0x0003)
-#define NIC_RAMCODE_VERSION_CFG_METHOD_35 (0x0010)
+#define NIC_RAMCODE_VERSION_CFG_METHOD_35 (0x0019)
 
 //hwoptimize
 #define HW_PATCH_SOC_LAN (BIT_0)

r8168-8.050.03.tar.gz/src/r8168_n.c -> r8168-8.051.02.tar.gz/src/r8168_n.c Changed

@@ -1922,8 +1922,8 @@
         data32 |= OCPR_Write | value;
 
         RTL_W32(tp, PHYOCP, data32);
-        for (i = 0; i < 100; i++) {
-                udelay(1);
+        for (i = 0; i < R8168_CHANNEL_WAIT_COUNT; i++) {
+                udelay(R8168_CHANNEL_WAIT_TIME);
 
                 if (!(RTL_R32(tp, PHYOCP) & OCPR_Flag))
                         break;
@@ -2005,12 +2005,12 @@
                                 (RegAddr & PHYAR_Reg_Mask) << PHYAR_Reg_shift |
                                 (value & PHYAR_Data_Mask));
 
-                        for (i = 0; i < 10; i++) {
-                                udelay(100);
+                        for (i = 0; i < R8168_CHANNEL_WAIT_COUNT; i++) {
+                                udelay(R8168_CHANNEL_WAIT_TIME);
 
                                 /* Check if the RTL8168 has completed writing to the specified MII register */
                                 if (!(RTL_R32(tp, PHYAR) & PHYAR_Flag)) {
-                                        udelay(20);
+                                        udelay(R8168_CHANNEL_EXIT_DELAY_TIME);
                                         break;
                                 }
                         }
@@ -2061,8 +2061,8 @@
         data32 <<= OCPR_Addr_Reg_shift;
 
         RTL_W32(tp, PHYOCP, data32);
-        for (i = 0; i < 100; i++) {
-                udelay(1);
+        for (i = 0; i < R8168_CHANNEL_WAIT_COUNT; i++) {
+                udelay(R8168_CHANNEL_WAIT_TIME);
 
                 if (RTL_R32(tp, PHYOCP) & OCPR_Flag)
                         break;
@@ -2145,13 +2145,13 @@
                         RTL_W32(tp, PHYAR,
                                 PHYAR_Read | (RegAddr & PHYAR_Reg_Mask) << PHYAR_Reg_shift);
 
-                        for (i = 0; i < 10; i++) {
-                                udelay(100);
+                        for (i = 0; i < R8168_CHANNEL_WAIT_COUNT; i++) {
+                                udelay(R8168_CHANNEL_WAIT_TIME);
 
                                 /* Check if the RTL8168 has completed retrieving data from the specified MII register */
                                 if (RTL_R32(tp, PHYAR) & PHYAR_Flag) {
                                         value = RTL_R32(tp, PHYAR) & PHYAR_Data_Mask;
-                                        udelay(20);
+                                        udelay(R8168_CHANNEL_EXIT_DELAY_TIME);
                                         break;
                                 }
                         }
@@ -2323,8 +2323,8 @@
 
                 RTL_W32(tp, OCPAR, (0x0F<<12) | (addr&0xFFF));
 
-                for (i = 0; i < 20; i++) {
-                        udelay(100);
+                for (i = 0; i < R8168_CHANNEL_WAIT_COUNT; i++) {
+                        udelay(R8168_CHANNEL_WAIT_TIME);
                         if (RTL_R32(tp, OCPAR) & OCPAR_Flag)
                                 break;
                 }
@@ -2346,7 +2346,7 @@
                 }
         }
 
-        udelay(20);
+        udelay(R8168_CHANNEL_EXIT_DELAY_TIME);
 
         return value2;
 }
@@ -2393,8 +2393,8 @@
                 RTL_W32(tp, OCPDR, value1);
                 RTL_W32(tp, OCPAR, OCPAR_Flag | (0x0F<<12) | (addr&0xFFF));
 
-                for (i = 0; i < 10; i++) {
-                        udelay(100);
+                for (i = 0; i < R8168_CHANNEL_WAIT_COUNT; i++) {
+                        udelay(R8168_CHANNEL_WAIT_TIME);
 
                         /* Check if the RTL8168 has completed ERI write */
                         if (!(RTL_R32(tp, OCPAR) & OCPAR_Flag))
@@ -2410,7 +2410,7 @@
                 }
         }
 
-        udelay(20);
+        udelay(R8168_CHANNEL_EXIT_DELAY_TIME);
 
         return 0;
 }
@@ -2634,36 +2634,56 @@
         }
 }
 
-void rtl8168_ephy_write(struct rtl8168_private *tp, int RegAddr, int value)
+static u8 rtl8168_check_ephy_addr(struct rtl8168_private *tp, int addr)
+{
+        if ( tp->mcfg != CFG_METHOD_35) goto exit;
+
+        if (addr & (BIT_6 | BIT_5))
+                rtl8168_clear_and_set_mcu_ocp_bit(tp, 0xDE28,
+                                                  (BIT_1 | BIT_0),
+                                                  (addr >> 5) & (BIT_1 | BIT_0));
+
+        addr &= 0x1F;
+
+exit:
+        return addr;
+}
+
+static void _rtl8168_ephy_write(struct rtl8168_private *tp, int addr, int value)
 {
         int i;
 
         RTL_W32(tp, EPHYAR,
                 EPHYAR_Write |
-                (RegAddr & EPHYAR_Reg_Mask) << EPHYAR_Reg_shift |
+                (addr & EPHYAR_Reg_Mask) << EPHYAR_Reg_shift |
                 (value & EPHYAR_Data_Mask));
 
-        for (i = 0; i < 10; i++) {
-                udelay(100);
+        for (i = 0; i < R8168_CHANNEL_WAIT_COUNT; i++) {
+                udelay(R8168_CHANNEL_WAIT_TIME);
 
                 /* Check if the RTL8168 has completed EPHY write */
                 if (!(RTL_R32(tp, EPHYAR) & EPHYAR_Flag))
                         break;
         }
 
-        udelay(20);
+        udelay(R8168_CHANNEL_EXIT_DELAY_TIME);
+}
+
+void rtl8168_ephy_write(struct rtl8168_private *tp, int addr, int value)
+{
+        _rtl8168_ephy_write(tp, rtl8168_check_ephy_addr(tp, addr), value);
 }
 
-u16 rtl8168_ephy_read(struct rtl8168_private *tp, int RegAddr)
+static u16 _rtl8168_ephy_read(struct rtl8168_private *tp, int addr)
 {
         int i;
         u16 value = 0xffff;
 
         RTL_W32(tp, EPHYAR,
-                EPHYAR_Read | (RegAddr & EPHYAR_Reg_Mask) << EPHYAR_Reg_shift);
+                EPHYAR_Read | (addr & EPHYAR_Reg_Mask) << EPHYAR_Reg_shift);
 
-        for (i = 0; i < 10; i++) {
-                udelay(100);
+        for (i = 0; i < R8168_CHANNEL_WAIT_COUNT; i++) {
+                udelay(R8168_CHANNEL_WAIT_TIME);
 
                 /* Check if the RTL8168 has completed EPHY read */
                 if (RTL_R32(tp, EPHYAR) & EPHYAR_Flag) {
@@ -2672,11 +2692,16 @@
                 }
         }
 
-        udelay(20);
+        udelay(R8168_CHANNEL_EXIT_DELAY_TIME);
 
         return value;
 }
 
+u16 rtl8168_ephy_read(struct rtl8168_private *tp, int addr)
+{
+        return _rtl8168_ephy_read(tp, rtl8168_check_ephy_addr(tp, addr));
+}
+
 static void ClearAndSetPCIePhyBit(struct rtl8168_private *tp, u8 addr, u16 clearmask, u16 setmask)
 {
         u16 EphyValue;
@@ -2732,8 +2757,8 @@
 
         RTL_W32(tp, CSIAR, cmd);
 
-        for (i = 0; i < 10; i++) {
-                udelay(100);
+        for (i = 0; i < R8168_CHANNEL_WAIT_COUNT; i++) {
+                udelay(R8168_CHANNEL_WAIT_TIME);
 
                 /* Check if the RTL8168 has completed CSI read */
                 if (RTL_R32(tp, CSIAR) & CSIAR_Flag) {
@@ -2742,7 +2767,7 @@
                 }
         }
 
-        udelay(20);
+        udelay(R8168_CHANNEL_EXIT_DELAY_TIME);
 
         return value;
 }
@@ -2774,15 +2799,15 @@

Changes of Revision 24